View AD1385_277113.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a
Stereo, 24-Bit, 192 kHz, Multibit DAC AD1853*
APPLICATIONS Hi End: DVD, CD, Home Theater Systems, Automotive Audio Systems, Sampling Musical Keyboards, Digital Mixing Consoles, Digital Audio Effects Processors
FEATURES 5 V Stereo Audio DAC System Accepts 16-/18-/20-/24-Bit Data Supports 24 Bits and 192 kHz Sample Rate Accepts a Wide Range of Sample Rates Including: 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz and 192 kHz Multibit Sigma-Delta Modulator with "Perfect Differential Linearity Restoration" for Reduced Idle Tones and Noise Floor Data Directed Scrambling DAC--Least Sensitive to Jitter Differential Output for Optimum Performance 120 dB Signal to Noise (Not Muted) at 48 kHz (A-Weighted Mono) 117 dB Signal to Noise (Not Muted) at 48 kHz (A-Weighted Stereo) 119 dB Dynamic Range (Not Muted) at 48 kHz Sample Rate (A-Weighted Mono) 116 dB Dynamic Range (Not Muted) at 48 kHz Sample Rate (A-Weighted Stereo) -107 dB THD+N (Mono Application Circuit, See Figure 30) -104 dB THD+N (Stereo) 115 dB Stopband Attenuation (96 kHz) On-Chip Clickless Volume Control Hardware and Software Controllable Clickless Mute Serial (SPI) Control for: Serial Mode, Number of Bits, Interpolation Factor, Volume, Mute, De-Emphasis, Reset Digital De-Emphasis Processing for 32, 44.1 and 48 kHz Sample Rates Clock Auto-Divide Circuit Supports Five Master-Clock Frequencies Flexible Serial Data Port with Right-Justified, LeftJustified, I2S-Compatible and DSP Serial Port Modes 28-Lead SSOP Plastic Package
PRODUCT OVERVIEW
The AD1853 is a complete high performance single-chip stereo digital audio playback system. It is comprised of a high performance digital interpolation filter, a multibit sigma-delta modulator, and a continuous-time current-out analog DAC section. Other features include an on-chip clickless stereo attenuator and mute capability, programmed through an SPIcompatible serial control port. The AD1853 is fully compatible with all known DVD formats and supports 48 kHz, 96 kHz and 192 kHz sample rates with up to 24 bits word lengths. It also provides the "Redbook" standard 50 s/15 s digital de-emphasis filters at sample rates of 32 kHz, 44.1 kHz and 48 kHz. The AD1853 has a very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers and sample rate converters. The AD1853 can be configured in left-justified, I2S, right-justified, or DSP serial port compatible modes. The AD1853 accepts serial audio data in MSB first, twos complement format. The AD1853 operates from a single +5 V power supply. It is fabricated on a single monolithic integrated circuit and is housed in a 28-lead SSOP package for operation over the temperature range 0C to +70C.
FUNCTIONAL BLOCK DIAGRAM
CONTROL DATA INPUT 3 DIGITAL SUPPLY 2 CLOCK IN
INT2
INT4
VOLUME MUTE
AD1853
DIGITAL DATA INPUT 2 ATTEN/ MUTE 8 FS INTERPOLATOR
SERIAL CONTROL INTERFACE MULTIBIT SIGMADELTA MODULATOR
VOLTAGE REFERENCE
AUTO-CLOCK DIVIDE CIRCUIT
IDAC ANALOG OUTPUTS
SERIAL MODE
SERIAL DATA INTERFACE
ATTEN/ MUTE
8 FS INTERPOLATOR
MULTIBIT SIGMADELTA MODULATOR
IDAC
2 RESET MUTE DE-EMPHASIS
2 ZERO FLAG
*Patents Pending.
ANALOG SUPPLY
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD1853-SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD) Ambient Temperature Input Clock Input Signal Input Sample Rate Measurement Bandwidth Word Width Input Voltage HI Input Voltage LO
+5.0 V +25C 24.576 MHz (512 x FS Mode) 996.094 kHz -0.5 dB Full Scale 48 kHz 20 Hz to 20 kHz 20 Bits 3.5 V 0.8 V
ANALOG PERFORMANCE (See Figures)
Min Resolution Signal-to-Noise Ratio (20 Hz to 20 kHz) No Filter (Stereo) No Filter (Mono--See Figure 30) With A-Weighted Filter (Stereo) With A-Weighted Filter (Mono--See Figure 30) Dynamic Range (20 Hz to 20 kHz, -60 dB Input) No Filter (Stereo) No Filter (Mono--See Figure 30) With A-Weighted Filter (Stereo) With A-Weighted Filter (Mono--See Figure 30) Total Harmonic Distortion + Noise (Stereo) Total Harmonic Distortion + Noise (Mono--See Figure 30) Analog Outputs Differential Output Range ( Full Scale w/1 mA into IREF) Output Capacitance at Each Output Pin Out-of-Band Energy (0.5 x FS to 75 kHz) CMOUT DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift Interchannel Crosstalk (EIAJ Method) Interchannel Phase Deviation Mute Attenuation De-Emphasis Gain Error
Typ 24 114 117 117 120
Max
Units Bits dB dB dB dB dB dB dB dB dB % dB % mA p-p pF dB V % dB ppm/C dB Degrees dB dB
107.5 110 -94
113 116 116 119 -104 0.00063 -107 0.00045 3.0 30 -90 2.75 3.0 0.01 25 -125 0.1 -100
-0.15
+0.15
0.1
NOTES Single-ended current output range: 1 mA 0.75 mA. Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Specifications subject to change without notice.
DIGITAL I/O (+25 C-AVDD, DVDD = +5.0 V
10%)
Min Input Voltage HI (VIH) Input Voltage LO (VIL) Input Leakage (IIH @ VIH = 3.5 V) Input Leakage (IIL @ VIL = 0.8 V) Input Capacitance Output Voltage HI (VOH) Output Voltage LO (VOL)
Specifications subject to change without notice.
Typ
Max 0.8 10 10 20
Units V V A A pF V V
2.4
DVDD-0.5
DVDD-0.4 0.2
0.5
-2-
REV. A
AD1853
POWER
Min Supplies Voltage, Analog and Digital Analog Current Digital Current Dissipation Operation--Both Supplies Operation--Analog Supply Operation--Digital Supply Power Supply Rejection Ratio 1 kHz 300 mV p-p Signal at Analog Supply Pins 20 kHz 300 mV p-p Signal at Analog Supply Pins
Specifications subject to change without notice.
Typ 5 12 28 200 60 140 -77 -72
Max 5.5 15 33
Units V mA mA mW mW mW dB dB
4.5
TEMPERATURE RANGE
Min Specifications Guaranteed Functionality Guaranteed Storage
Specifications subject to change without notice.
Typ 25
Max 70 125
Units C C C
0 -55
DIGITAL FILTER CHARACTERISTICS
Sample Rate (kHz) 44.1 48 96 192
Passband (kHz) DC-20 DC-21.8 DC-39.95 DC-87.2
Stopband (kHz) 24.1-328.7 26.23-358.28 56.9-327.65 117-327.65
Stopband Attenuation (dB) 110 110 115 95
Passband Ripple (dB) 0.0002 0.0002 0.0005 +0/-0.04 (DC-21.8 kHz) +0/-0.5 (DC-65.4 kHz) +0/-1.5 (DC-87.2 kHz)
Specifications subject to change without notice.
GROUP DELAY
Chip Mode INT8x Mode INT4x Mode INT2x Mode
Group Delay Calculation 5553/(128 x FS) 5601/(64 x FS) 5659/(32 x FS)
FS 48 kHz 96 kHz 192 kHz
Group Delay 903.8 911.6 921
Units s s s
Specifications subject to change without notice.
DIGITAL TIMING (Guaranteed Over 0 C to +70 C, AVDD = DVDD = +5.0 V
10%)
Min tDMP tDML tDMH tDBH tDBL tDBP tDLS tDLH tDDS tDDH tPDRP MCLK Period (With FMCLK = 256 x FLRCLK)* MCLK LO Pulsewidth (All Modes) MCLK HI Pulsewidth (All Modes) BCLK HI Pulsewidth BCLK LO Pulsewidth BCLK Period LRCLK Setup LRCLK Hold (DSP Serial Port Mode Only) SDATA Setup SDATA Hold PD/RST LO Pulsewidth 54 0.4 x tDMP 0.4 x tDMP 20 20 140 20 5 5 10 5
Units ns ns ns ns ns ns ns ns ns ns ns
*Higher MCLK frequencies are allowable when using the on-chip Master Clock Auto-Divide feature. Specifications subject to change without notice.
REV. A
-3-
AD1853
ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION
Min DVDD to DGND AVDD to AGND Digital Inputs Analog Outputs AGND to DGND Reference Voltage Soldering -0.3 -0.3 DGND - 0.3 AGND - 0.3 -0.3
Max 6 6 DVDD + 0.3 AVDD + 0.3 0.3 (AVDD + 0.3)/2 +300 10
Units V V V V V C sec
DGND 1 MCLK 2 CLATCH 3 CCLK 4 CDATA 5 INT4 INT2
6 7 28 27 26 25 24
DVDD SDATA BCLK L/RCLK RST MUTE
AD1853
23
TOP VIEW 22 ZEROL ZEROR 8 (Not to Scale) 21 IDPM0 DEEMP 9 IREF 10 AGND 11 OUTL+ 12 OUTL- 13
20 19 18 17 16 15
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
IDPM1 FILTB AVDD OUTR+ OUTR- FCR
PACKAGE CHARACTERISTICS
FILTR 14
Min JA (Thermal Resistance [Junction-to-Ambient]) JC (Thermal Resistance [Junction-to-Case])
Typ 109 39
Max
Units C/W C/W
ORDERING GUIDE
Model AD1853JRS AD1853JRSRL
Temperature 0C to +70C 0C to +70C
Package Description 28-Lead Shrink Small Outline 28-Lead Shrink Small Outline
Package Options RS-28 RS-28 on 13" Reels
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1853 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. A
AD1853
PIN FUNCTION DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 9
Input/Output I I I I I I I O I
Pin Name DGND MCLK CLATCH CCLK CDATA INT4x INT2x ZEROR DEEMP
Description Digital Ground. Master Clock Input. Connect to an external clock source. See Table II for allowable frequencies. Latch input for control data. This input is rising-edge sensitive. Control clock input for control data. Control input data must be valid on the rising edge of CCLK. CCLK may be continuous or gated. Serial control input, MSB first, containing 16 bits of unsigned data. Used for specifying control information and channel-specific attenuation. Assert HI to select interpolation ratio of 4x, for use with double-speed inputs (88 kHz or 96 kHz). Assert LO to select 8x interpolation ratio. Assert HI to select interpolation ratio of 2x, for quad-speed inputs (176 kHz or 192 kHz). Assert LO to select 8x interpolation ratio. Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal input for more than 1024 LR Clock Cycles. De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used to impose a 50 s/15 s response characteristic on the output audio spectrum at an assumed 44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected via SPI control register. Connection point for external bias resistor. Voltage held at VREF. Analog Ground. Left Channel Positive line level analog output. Left Channel Negative line level analog output. Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference with parallel 10 F and 0.1 F capacitors to the AGND (Pin 11). Filter cap return pin for cap connected to FILTB (Pin 19). Right Channel Negative line level analog output. Right Channel Positive line level analog output. Analog Power Supply. Connect to analog +5 V supply. Filter Capacitor connection, connect 10 F capacitor to FCR (Pin 15). Input serial data port mode control one. With IDPM0, defines one of four serial modes. Input serial data port mode control zero. With IDPM1, defines one of four serial modes. Left Channel Zero Flag output. This pin goes HI when Left Channel has no signal input for more than 1024 LR Clock Cycles. Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation. Reset. The AD1853 is placed in a reset state when this pin is held LO. The AD1853 is reset on the rising edge of this signal. The serial control port registers are reset to the default values. Connect HI for normal operation. Left/Right clock input for input data. Must run continuously. Bit clock input for input data. Serial input, MSB first, containing two channels of 16/18/20/24 bit twos-complement data. Digital Power Supply Connect to digital +5 V supply.
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
I I O O O I O O I O I I O I I
IREF AGND OUTL+ OUTL- FILTR FCR OUTR- OUTR+ AVDD FILTB IDPM1 IDPM0 ZEROL MUTE RST
25 26 27 28
I I I I
L/RCLK BCLK SDATA DVDD
REV. A
-5-
AD1853
L/RCLK INPUT BCLK INPUT SDATA INPUT LEFT CHANNEL RIGHT CHANNEL
LSB
MSB
MSB-1 MSB-2
LSB+2 LSB+1
LSB
MSB
MSB-1 MSB-2
LSB+2 LSB+1
LSB
Figure 1. Right-Justified Mode
L/RCLK INPUT BCLK INPUT SDATA INPUT
LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB-1 MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1 MSB-2
LSB+2 LSB+1
LSB
MSB
Figure 2. I2S-Justified Mode
L/RCLK INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK INPUT SDATA INPUT
MSB
MSB-1 MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1 MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
Figure 3. Left-Justified Mode
L/RCLK INPUT BCLK INPUT SDATA INPUT
LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB-1
LSB+2
LSB+1
LSB
MSB
MSB-1
LSB+2
LSB+1
LSB
MSB
MSB-1
Figure 4. Left-Justified DSP Mode
L/RCLK INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK INPUT SDATA INPUT
LSB
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
Figure 5. 32 x FS Packed Mode
-6-
REV. A
AD1853
OPERATING FEATURES Serial Data Input Port
The AD1853's flexible serial data input port accepts data in twos-complement, MSB-first format. The left channel data field always precedes the right channel data field. The serial mode is set by using either the external mode pins (IDPM0 Pin 21 and IDPM1 Pin 20) or the mode select bits (Bits 4 and 5) in the SPI control register. To control the serial mode using the external mode pins, the SPI mode select bits should be set to zero (default at power-up). To control the serial mode using the SPI mode select bits, the external mode control pins should be grounded. In all modes except for the right-justified mode, the serial port will accept an arbitrary number of bits up to a limit of 24 (extra bits will not cause an error, but they will be truncated internally). In the right-justified mode, control register Bits 8 and 9 are used to set the word length to 16, 20, or 24 bits. The default on power-up is 24-bit mode. When the SPI Control Port is not being used, the SPI pins (3, 4 and 5) should be tied LO.
Serial Data Input Mode
Figure 1 shows the right-justified mode. LRCLK is HI for the left channel, LO for the right channel. Data is valid on the rising edge of BCLK. In normal operation, there are 64-bit clocks per frame (or 32 per half-frame). When the SPI word length control bits (Bits 8 and 9 in the control register) are set to 24 bits (0:0), the serial port will begin to accept data starting at the 8th bit clock pulse after the L/RCLK transition. When the word length control bits are set to 20-bit mode, data is accepted starting at the 12th bit clock position. In 16-bit mode, data is accepted starting at the 16th-bit clock position. These delays are independent of the number of bit clocks per frame, and therefore other data formats are possible using the delay values described above. For detailed timing, see Figure 6. Figure 2 shows the I2S mode. L/RCLK is LO for the left channel, and HI for the right channel. Data is valid on the rising edge of BCLK. The MSB is left-justified to an L/RCLK transition but with a single BCLK period delay. The I2S mode can be used to accept any number of bits up to 24. Figure 3 shows the left-justified mode. L/RCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. The MSB is left-justified to an L/RCLK transition, with no MSB delay. The left-justified mode can accept any word length up to 24 bits. Figure 4 shows the DSP serial port mode. L/RCLK must pulse HI for at least one bit clock period before the MSB of the left channel is valid, and L/RCLK must pulse HI again for at least one bit clock period before the MSB of the right channel is valid. Data is valid on the falling edge of BCLK. The DSP serial port mode can be used with any word length up to 24 bits.
The AD1853 uses two multiplexed input pins to control the mode configuration of the input data port mode.
Table I. Serial Data Input Modes
IDPM1 (Pin 20) 0 0 1 1
IDPM0 (Pin 21) 0 1 0 1
Serial Data Input Format Right Justified (24 Bits) Default I2S-Compatible Left Justified DSP
tDBH
BCLK
tDBP
tDBL tDLS
L/RCLK
SDATA LEFT-JUSTIFIED MODE
tDDS
MSB MSB-1
tDDH
SDATA I2S-JUSTIFIED MODE
tDDS
MSB
tDDH
SDATA RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 16-BIT CLOCKS (16-BIT DATA)
tDDS
MSB
tDDS
LSB
tDDH
tDDH
Figure 6. Serial Data Port Timing
REV. A
-7-
AD1853
Table II.
Chip Mode INT8x Mode INT4x Mode INT2x Mode
Allowable Master Clock Frequencies 256 x FS, 384 x FS, 512 x FS, 768 x FS, 1024 x FS 128 x FS, 192 x FS, 256 x FS, 384 x FS, 512 x FS 64 x FS, 96 x FS, 128 x FS, 192 x FS, 256 x FS
Nominal Input Sample Rate 48 kHz 96 kHz 192 kHz
Internal Sigma-Delta Clock Rate 128 x FS 64 x FS 32 x FS
In this mode, it is the responsibility of the DSP to ensure that the left data is transmitted with the first LRCLK pulse, and that synchronism is maintained from that point forward. Note that the AD1853 is capable of a 32 x FS BCLK frequency "packed mode" where the MSB is left-justified to an L/RCLK transition, and the LSB is right-justified to the opposite L/RCLK transition. L/RCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. Packed mode can be used when the AD1853 is programmed in rightjustified or left-justified mode. Packed mode is shown is Figure 5.
Master Clock Auto-Divide Feature
CLATCH is used internally to latch the parallel data from the serial-to-parallel converter. This rising edge should be aligned with the falling edge of the last CCLK pulse in the 16-bit frame. The CCLK can run continuously between transactions. The serial control data is 16-bit MSB first, and is unsigned. Bits 0 and 1 are used to select 1 of 3 registers (control, volume left, and volume right). The remaining 14 bits (bits 15:2) are used to carry the data for the selected register. If a volume register is selected, then the upper 14 bits are used to multiply the digital input signal by the control word, which is interpreted as an unsigned number (for example, 11111111111111 is 0 dB, and 01111111111111 is -6 dB, etc.). The default volume control words on power-up are all 1s (0 dB). The control register only uses bits 11:2 to carry data; the upper bits (15:12) should always be written with zeroes, as several test modes are decoded from these upper bits. The control register defaults on power-up to 8x interpolation mode, 24-bit right-justified serial mode, unmuted, and no de-emphasis filter. The intent with these reset defaults is to enable AD1853 applications without requiring the use of the serial control port. For those users that do not use the serial control port, it is still possible to mute the AD1853 output by using the MUTE pin (Pin 23) signal. Note that the serial control port timing is asynchronous to the serial data port timing. Changes made to the attenuator level will be updated on the next edge of the LRCLK after CLATCH write pulse as shown in Figure 6.
The AD1853 has a circuit that autodetects the relationship between master clock and the incoming serial data, and internally sets the correct divide ratio to run the interpolator and modulator. The allowable frequencies for each mode are shown above.
Serial Control Port
The AD1853 serial control port is SPI-compatible. SPI (Serial Peripheral Interface) is an industry standard serial port protocol. The write-only serial control port gives the user access to: select input mode, soft reset, soft de-emphasis, channel specific attenuation and mute (both channels at once). The SPI port is a 3-wire interface with serial data (CDATA), serial bit clock (CCLK), and data latch (CLATCH). The data is clocked into an internal shift register on the rising edge of CCLK. The serial data should change on the falling edge of CCLK and be stable on the rising edge of CCLK. The rising edge of
t CHD
CDATA D15 D14 D0
t CCH
CCLK
t CCL
CLATCH
t CSU
t CLL
t CLH
Figure 7. Serial Control Port Timing
-8-
REV. A
AD1853
Table III. Digital Timing
Min tCCH tCCL tCSU tCHD tCLL tCLH CCLK HI Pulsewidth CCLK LOW Pulsewidth CDATA Setup Time CDATA Hold Time CLATCH LOW Pulsewidth CLATCH HI Pulsewidth 40 40 10 10 10 10
Units ns ns ns ns ns ns
SPI REGISTER DEFINITIONS
VOLUME LEFT and VOLUME RIGHT Registers
The SPI port allows flexible control of many chip parameters. It is organized around three registers; a LEFT-CHANNEL VOLUME register, a RIGHT-CHANNEL VOLUME register and a CONTROL register. Each WRITE operation to the AD1853 SPI control port requires 16 bits of serial data in MSB-first format. The bottom two bits are used to select one of three registers, and the top 14 bits are then written to that register. This allows a write to one of the three registers in a single 16-bit transaction. The SPI CCLK signal is used to clock in the data. The incoming data should change on the falling edge of this signal. At the end of the 16 CCLK periods, the CLATCH signal should rise to latch the data internally into the AD1853.
Register Addresses
A write operation to the left or right volume registers will activate the "auto-ramp" clickless volume control feature of the AD1853. This feature works as follows. The upper 10 bits of the volume control word will be incremented or decremented by 1 at a rate equal to the input sample rate. The bottom 4 bits are not fed into the auto-ramp circuit and thus take effect immediately. This arrangement gives a worst-case ramp time of about 1024/FS for step changes of more than 60 dB, which has been determined by listening tests to be optimal in terms of preventing the perception of a "click" sound on large volume changes. See Figure 8 for a graphical description of how the volume changes as a function of time. The 14-bit volume control word is used to multiply the signal, and therefore the control characteristic is linear, not dB. A constant dB/step characteristic can be obtained by using a lookup table in the microprocessor that is writing to the SPI port.
The lowest two bits of the 16-bit input word are decoded as follows to set the register into which the upper 14 bits will be written. Bit 1 0 1 0 Bit 0 0 0 1 Register
0 VOLUME REQUEST REGISTER
LEVEL - dB
Volume Left Volume Right Control Register
-60
0 ACTUAL VOLUME REGISTER
-60 TIME
20ms
Figure 8. Smooth Volume Control
REV. A
-9-
AD1853
Control Register
The following table shows the functions of the control register. The control register is addressed by having a "01" in the bottom 2 bits of the 16-bit SPI word. The top 14 bits are then used for the control register. Bit 11 INT2x Mode OR'd with Pin. Default = 0 Bit 10 INT4x Mode OR'd with Pin. Default = 0 Bit 9:8 Number of Bits in RightJustified Serial Mode. 0:0 = 24 0:1 = 20 1:0 = 16 Default = 0:0 Bit 7 Soft Reset. Default = 0 Bit 6 Bit 5:4 Bit 3:2 De-Emphasis Filter Select. 0:0 No Filter 0:1 44.1 kHz Filter 1:0 32 kHz Filter 1:1 48 kHz Filter Default = 0.0
Soft Mute OR'd Serial Mode OR'd with Pin. with Mode Pins. Default = 0 IDPMI:IDPM0 0:0 Right-Justified 0:1 I2S 1:0 Left-Justified 1:1 DSP Mode Default = 0:0
De-Emphasis
Mute
The AD1853 offers two methods of muting the analog output. By asserting the MUTE (Pin 23) signal HI, both the left and right channel are muted. As an alternative, the user can assert the mute bit in the serial control register (Bit 6) HI. The AD1853 has been designed to minimize pops and clicks when muting and unmuting the device by automatically "ramping" the gain up or down. When the device is unmuted, the volume returns to the value set in the volume register.
Analog Attenuation
The AD1853 has a built-in de-emphasis filter that can be used to decode CDs that have been encoded with the standard "Redbook" 50 s/15 s emphasis response curve. Three curves are available; one each for 32 kHz, 44.1 kHz and 48 kHz sampling rates. The external "DEEMP" pin (Pin 9) turns on the 44.1 kHz de-emphasis filter. The other filters may be selected by writing to control Bits 2 and 3 in the control register. If the SPI port is used to control the de-emphasis filter, the external DEEMP pin should be tied LO.
Control Signals
The AD1853 also offers the choice of using IREF (Pin 10) to attenuate by up to 50 dB in the analog domain. This feature can be used as an analog volume control. It is also a convenient place to add a compressor/limiter gain control signal.
Output Drive, Buffering and Loading
The AD1853 analog output stage is able to drive a 1 k (in series with 2 nF) load. The analog outputs are usually ac coupled with a 10 F capacitor.
The IDPM0 and IDPM1 control inputs are normally connected HI or LO to establish the operating state of the AD1853. They can be changed dynamically (and asynchronously to LRCLK and the master clock), but it is possible that a click or pop sound may result during the transition from one serial mode to another. If possible, the AD1853 should be placed in mute before such a change is made.
Figures 9-14 show the calculated frequency response of the digital interpolation filters. Figures 15-27 show the performance of the AD1853 as measured by an Audio Precision System 2 Cascade. For the wideband plots, the noise floor shown in the
plots is higher than the actual noise floor of the AD1853. This is caused by the higher noise floor of the "High Bandwidth" ADC used in the Audio Precision measurement system. The two-tone test shown in Figure 18 is per the SMPTE standard for measuring Intermodulation Distortion.
0 -20 -40
ATTENUATION - dB
0.001 0.0008 0.0006 0.0004 0.0002 dB 0
-60 -80 -100 -120
-0.0002 -0.0004 -0.0006 -0.0008 -0.001 0 2 4 6 10 12 14 8 FREQUENCY - kHz 16 18 20
-140 -160 0 50 100 150 200 250 FREQUENCY - kHz 300 350
Figure 9. Passband Response 8x Mode, 48 kHz Sample Rate
Figure 10. Complete Response, 8x Mode, 48 kHz Sample Rate
-10-
REV. A
Typical Performance Characteristics-AD1853
0.5 0.4
0 -20
0.3
-40
0.2 0.1
-60
dB
dB
0 -0.1 -0.2 -0.3 -0.4 -0.5 -10
-80 -100 -120 -140 -160 0 50 100 150 200 FREQUENCY - kHz 250 300
5
10
15 20 25 30 FREQUENCY - kHz
35
40
Figure 11. 44 kHz Passband Response 4x Mode, 96 kHz Sample Rate
Figure 14. Complete Response, 4x Mode, 96 kHz Sample Rate
2.0 1.5 1.0 0.5
0 -20 -40 -60
dB
0 -0.5 -1.0 -1.5 -2.0
dB
0 10 20 30 40 50 60 FREQUENCY - kHz 70 80
-80 -100 -120 -140 -160 0 50 100 150 FREQUENCY - kHz 200 250
Figure 12. 88 kHz Passband Response 2x Mode, 192 kHz Sample Rate
Figure 15. Complete Response, 2x Mode, 192 kHz Sample Rate
-50 -60
0 -10 -20
-70 -80
-30 -40
dBr
dB
-90 -100 -110 -120 10
-50 -60 -70 -80 -90
-100 100 1k FREQUENCY - Hz 10k -110 -120 -100 -80 -60 dBFS -40 -20 0
Figure 13. THD vs. Frequency Input @ -3 dBFS, SR 48 kHz
Figure 16. THD + N Ratio vs. Amplitude Input 1 kHz, SR 48 kHz, 24-Bit
REV. A
-11-
AD1853
2 -90 -100 0
-2 -4
-110 -120
dBr
-6
dBr
-130 -140 -150 -160 0 2 4 6 8 10 12 14 FREQUENCY - kHz 16 18 20 22 -8 -10 -12 10 100 1k FREQUENCY - Hz 10k
Figure 17. Normal De-Emphasis Frequency Response Input @ -10 dBFS, SR 48 kHz
Figure 20. Noise Floor for Zero Input, SR 48 kHz, SNR -117 dBFS A-Weighted
-10 -30
0 -10 -20 -30 -40 -50 -60
-50 -70
dBr
dBr
-90 -110 -130 -150 0 2 4 6 8 10 12 14 FREQUENCY - kHz 16 18 20 22
-70 -80 -90 -100 -110 -120 -130 -140 -150 0 2 4 6 8 10 12 14 FREQUENCY - kHz 16 18 20 22
Figure 18. SMPTE/DIN 4:1 IMD 60 Hz/7 kHz @ 0 dBFS
Figure 21. Input 0 dBFS @ 1 kHz, BW 10 Hz to 22 kHz, SR 48 kHz, THD+N 104 dBFS
0
-50 -60
-20 -70 -40 -80 -90 -60
dBr
dBr
-80 -120 -100 -80 dBFS -60 -40 -20 0
-100 -110 -120
-100 -120 -140 -140
-130 -140 -150 -160 0 2 4 6 8 10 12 14 FREQUENCY - kHz 16 18 20 22
Figure 19. Linearity vs. Amplitude Input 200 Hz, SR 48 kHz, 24-Bit Word
Figure 22. Dynamic Range for 1 kHz @ -60 dBFS, 116 dB, Triangular Dithered Input
-12-
REV. A
AD1853
-60 0 -10 -20 -30 -70 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -100 10 100 1k FREQUENCY - Hz 10k -160 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 FREQUENCY - kHz
dBr
-80
-90
Figure 23. Power Supply Rejection vs. Frequency AVDD 5 V dc + 100 mV p-p ac
Figure 26. Wideband Plot, 25 kHz Input, 2x Interpolation, SR 192 kHz
0 -10 -20 -30 -40 -50 -60
dBr dBr
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 40 60 80 FREQUENCY - kHz 100 120 -160 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 FREQUENCY - kHz
dBr
-70 -80 -90 -100 -110 -120 -130 -140
Figure 24. Wideband Plot, 15 kHz Input, 8x Interpolation, SR 48 kHz
Figure 27. Wideband Plot, 75 kHz Input, 2x Interpolation, SR 192 kHz
0 -10 -20 -30 -40 -50 -60
dBr
-70 -80 -90 -100 -110 -120 -130 -140 20 40 60 80 FREQUENCY - kHz 100 120
Figure 25. Wideband Plot, 37 kHz Input, 4x Interpolation, SR 96 kHz
REV. A
-13-
AD1853
STEREO MODE OUTPUT FILTER
HDR2 DVDD 1 EXT SDATA EXT L/RCLK EXT SCLK EXT MCLK DVDD R17 10k R25 100 R13 10k C35 47pF R26 100 R14 10k C36 47pF R27 100 R15 10k C34 47pF S2B 9 IDPM0 2 S2C DVDD R18 10k 8 IDPM1 3 HDR3 FN 44/48 96 192 NO DVDD R6 10k DVDD C11 100nF DVDD DVDD SPDIF/EXT 10 1 C5 100nF FB2 600Z R5 10k 1 0 1 0 1 2 0 0 1 1
EXT I/F IN
R24 100 R12 10k C37 47pF
SAMPLE RATE MODE
HDR3
SPDIF/EXT R11 10k I/F SELECT
S2A
U4 PALCE22V10-J
C6 100nF EXT MCLK EXT SCLK EXT L/RCLK EXT SDATA CLK/I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I /O9 I/O8 I /O7 I /O6 I /O5 I /O4 I /O3 I /O2 I/O1 I/O 0
1
0
U2 DATA SOURCE 1 2 I2S SERIAL DATA MODE 3 DEEMPH OFF 4 MUTE OFF 5
S2A S2B S2C S2D S2E
VA+
VD+ SDATA FSYNC SCK MCK FS 64FS 256FS
J1
SIGNAL SOURCE
1 R1 75 C2 10nF S1 C1 10nF RXP
DVDD C9 100nF
AVDD C8 100nF
SPNIF IN
0
U2 CS8414-CS
RXN M0 M1 M2 M3 C
DVDD AVDD
U5 AD1853JRS
INT4 INT2 SDATA OUTR- ROUT- OUTR+ ROUT+
500mVp-p DVDD FB1 600Z C4 100nF R2 3.40k
U CBL VERF ERF C0/E0 Ca/E1 Cb/E2 Cc/F0 Cd/F1 Ce/F2 SEL CSI2/FCK AGND DGND PREEMPH R19 VREF 10k
R23 274
DS4
DVDD VERF
L/RCLK BCLK OUTL+ LOUT+ MCLK IDPM0 MCLK IDPM1 DEEMP MUTE CLATCH CCLK CDATA ZEROR ZEROL RST DGND FCR AGND AGND FB3 600Z C10 100nF R20 11 274 DS1 ZERO LEFT DS2 ZERO RIGHT SET Ib = 1mA DVDD FILTB C26 + 10 F - C56 100nF R28 2.67k FILTR IREF VREF +2.7V OUTL- LOUT-
Q1 2N2222
U3A 74HC00D 1 2
CLATCH 3 CCLK CDATA ZR ZL RST
DVDD TOSLINK IN OUT
FILT R4 1k R3 750 C24 47nF
U1 TORX173
SHLD DGND
DVDD
DGND
DGND
DVDD R16 10k OFF DEEMPH ON 7 S2D 4 R10 10k
DEEMPH MUTE ZL
U3D 74HC00D 12 13
ON MUTE
OFF 6 S2E 5
HDR1 DVDD 1 CDATA EXT C I/F CCLK CLATCH MCLK U3B 74HC00D 4 6 5 ZR
U3C 74HC00D R21 9 8 274 10
NOTE: = DGND = AGND
DVDD R22 274 DS3 DEEMPH
DVDD C12 100nF
R7 10k
R8 10k
R9 10k
#98107-02-3 REV. 1.1
Figure 28. Digital Receiver, MUX and AD1853 DAC
-14-
REV. A
AD1853
R48 4.12k
OUTPUT BUFFERS AND LP FILTERS
-AVSS C46 330pF, NP0 C23 100nF ROUT+ C52* NP C57 220pF NP0 R33 2.74k R34 2.74k R29 2.94k
C38 220pF NP0
U6A OP275
C21 100nF C43 680pF NP0
R41 604
U8B
+AVCC
1 R43 49.9k
J2 RIGHT OUT 0
ROUT- C53* NP R52 402 VREF +2.7V C7 100nF R49 4.12k
OP275 U6B
C47 330pF, NP0
R35 2.74k
C42 680pF NP0 R36 2.74k
R30 2.94k C39 220pF NP0
OP275
C50 2.2nF NP0
+ C25 - 10 F
R50 4.12k
GAUSSIAN FILTER RESPONSE -3dB CORNER FREQUENCY: 75kHz
R53 402 LOUT+
-AVEE C48 330pF, NP0 C22 100nF R37 2.74k R38 2.74k R31 2.94k
C54* NP C58 220pF NP0
C40 220pF NP0 -AV SS C18 100nF R42 604 J3 LEFT OUT 0
U7A OP275
C20 100nF C45 680pF NP0
U8A
+AVCC
1 R44 49.9k
LOUT- C55* NP
OP275 U7B
C49 330pF, NP0 *NOT POPULATED R51 4.12k
R39 2.74k
C44 680pF NP0
OP275
R32 2.94k C19 100nF
C51 2.2nF NP0
R40 2.74k
C41 +AVCC 220pF NP0
RESET GENERATOR
DVDD +15V dc C17 100nF VCC J6
VOLTAGE REGULATORS AND SUPPLY FILTERING
U11 ADP3303-5.0 IN CR2 1SMB15AT3 RST J7 0V AGND J8 -15V dc U9 LM317 +5V REG VIN C27 10 F + - C13 100nF VOUT R45 243 C14 100nF DVDD GND C15 100nF + C30 - 10 F IN ERR SD OUT OUT NR GND C16 100nF C3 10nF +5V REG AVDD R47 332 + C31 - 10 F AGND + C33 - 10 F -AVSS DS5 + C32 - 10 F +AVCC
FB4 600Z
U10 ADM707AR
PFI MR S3 RESET RESET PFO GND
POWER
RESET
CR3 +9V dc J4 1N4001 TO +15V dc NOTE: = DGND = AGND 0V DGND CR1 1SMB15AT3 J5
FB5 600Z
+ C28 - 10 F
R46 715
+ C29 - 10 F DGND
Figure 29. DAC Output LP Filter, Power and Reset
REV. A
-15-
AD1853
I/V CONVERTERS AND LP FILTER
R9* 2.87k C6 68pF, NP0 R11 100 GAUSSIAN FILTER RESPONSE -3dB CORNER FREQUENCY: 75kHz
PIN 12 LOUT+ PIN 13 LOUT-
R3 2.74k
R4 2.74k
R1 2.94k
C1 220pF NP0
U2 AD797
C4 680pF NP0 R7 604 C5 2.2nF NP0 R8 49.9k J1 OUT 6Vrms 0
U1
R5 2.74k PIN 17 ROUT+ PIN 16 ROUT- VREF +2.78V C8 100nF C3 680pF R2 NP0 2.94k R6 2.74k C2 220pF NP0
1
AD797
U3 AD797
C7 R12 68pF, NP0 100 R10* 2.87k
+ C15 10 F - TANT
NOTES: 1. R9, R10 MUST BE LOW NOISE TYPES. METAL FILM IS RECOMMENDED. 2. RIGHT CHANNEL DIGITAL DATA MUST BE INVERTED. J2 +AVCC +16.5V dc C10 100nF C12 100nF C14 100nF + C16 10 F - TANT + C17 10 F - TANT J3 0V AGND J4 -16.5V dc
NOTE: = AGND
C9 100nF -AVSS
C11 100nF
C13 100nF
Figure 30. Mono Application Circuit
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Shrink Small Outline Package (SSOP) (RS-28)
0.407 (10.34) 0.397 (10.08)
28
15
0.311 (7.9) 0.301 (7.64)
1 14
0.212 (5.38) 0.205 (5.21)
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC
8 0.015 (0.38) 0 SEATING 0.009 (0.229) 0.010 (0.25) PLANE 0.005 (0.127)
0.03 (0.762) 0.022 (0.558)
-16-
REV. A
PRINTED IN U.S.A.
C3503a-8-4/99

▲Up To Search▲

Price & Availability of AD1385

	To Download AD1385 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .